1. Field of the Invention
The present invention relates generally to communications systems. More particularly, the present invention relates to trellis encoding for discrete multitone transceivers.
2. Background
The recent explosion of the Internet has created an intense need for a higher data transmission rate. Applications such as web surfing, e-mail, news-group, chat rooms, and the like, have become a common part of many people""s lives. As the demand grows and applications such as multicast video-on-demand, high-resolution Internet gaming, and video conferencing become more commonplace, the traditional modems do not have enough bandwidth to serve such needs. As a result, the broadband digital subscriber line (xe2x80x9cDSLxe2x80x9d) modems that use a bandwidth beyond the voice band have become a key to future broadband access.
Among the many DSL technologies, asymmetric DSL (xe2x80x9cADSLxe2x80x9d) is one of the most popular choices in meeting the broadband access needs. Reasons for this include coexistence with the plain old telephone service (xe2x80x9cPOTSxe2x80x9d), based on existing wired infrastructure, substantial availability for the current POTS subscribers, up to 8 Mbits/sec downstream speed and 640 kbits/sec upstream speed, and always connected.
ADSL uses the existing local loop to deliver high-bandwidth services. At each end of the circuit, modems are installed, which make possible the promise of ADSL. These modems create a high-bandwidth downstream channel, a smaller upstream channel and a basic telephone service channel for voice. The actual bandwidth provided is dependent on the length of the local loop. In a typical ADSL installation, service modules (set-top boxes, routers, PC interface devices) attach at the customer premises to the premises distribution network (xe2x80x9cPDNxe2x80x9d). The PDN is the premises wiring scheme that interconnects customer premises equipment to the local loop. The PDN is attached to a remote ADSL transmission unit (xe2x80x9cATU-Rxe2x80x9d), which in turn is connected to the local loop using a splitter. The splitter performs the logical separation of voice and data traffic.
At the network side of the circuit, the loop terminates at another voice-data splitter, which in turn is connected to a central ADSL transmission unit (xe2x80x9cATU-Cxe2x80x9d). The ATU-C is connected to the access node, which is the aggregation point for broadband and narrowband data sources delivered from a DSL access multiplexer (xe2x80x9cDSLAMxe2x80x9d). DSLAM allows TV signals, interactive video, Internet access and a wide variety of other data types to share access to the ADSL-equipped local loop.
ADSL relies on frequency division multiplexing to create the independent basic telephone service, upstream and downstream channels. ADSL establishes a channel at the low end of the spectrum for voice; a medium frequency band for the upstream channel; and a higher frequency band for the high-bandwidth downstream channel. In some cases, the channels may overlap. This technique is called partially overlapped echo-canceled transmission (xe2x80x9cPOETxe2x80x9d).
Two signal modulation techniques have been developed for use in ADSL implementations to achieve the very high bit rates that the service promises. The first, called carrierless amplitude phase modulation (xe2x80x9cCAPxe2x80x9d), is similar to quadrature amplitude modulation (xe2x80x9cQAMxe2x80x9d), a technique that has been in existence for quite some time. The second technique used in ADSL systems is called discrete multitone (xe2x80x9cDMTxe2x80x9d). In DMT, the 1.1 MHz channel is broken into 256 4-kHz sub-channels, hence the term, xe2x80x9cmultitone.xe2x80x9d Each sub-channel has its own carrier, and the signal-to-noise ratio is constantly monitored by the DMT system to determine how many bits-per-tone can be carried in each sub-channel. The DMT system dynamically adjusts each channel, thus, resulting in a technique that is by its very nature dynamically rate adaptive. If certain frequency ranges in the spectrum of sub-channels are noisy, they are not used. DMT is the broadly accepted coding standard for ADSL, and is significantly more complex than CAP.
Four-dimensional trellis coded modulation (xe2x80x9c4D-TCMxe2x80x9d) is a coding technique that is used to enhance the overall performance of DMT-based transceivers for ADSL. The basic idea of 4D-TCM is to combine coding and modulation. 4D-TCM consists of a convolutional code that adds forward error correction to the DMT modulation scheme by adding an additional bit to each baud. Convolutional coding is used to introduce a dependency between successive signal points such that only certain patterns or sequences of signal points are permitted.
FIG. 1a illustrates a conventional modulation and encoding system 100 of an ADSL modem. FIFO 110 receives and buffers an input bit stream 105 of data bits for each DMT tone. The number of bits carried by a DMT tone are determined based on the signal-to-noise ratio. As stated above, each DMT tone might carry a different number of data bits, ranging from 0 to 15, depending upon each particular sub-channel condition.
Four-dimensional TCM encoding is performed on each consecutive pair of tones. For purposes of describing the conventional modulation and encoding method, b1 denotes the number of bits in the first tone and b2 denotes the number of bits in the second tone, where b2xe2x89xa7b1, according to ADSL standard. The conventional method retrieves b1 and b2 (whose derivation is not described here), for example, from a lookup table. For the downstream direction, the lookup table may include 256 entries, i.e., one entry per each sub-channel or tone. Now, once b2 and b1 are retrieved, the modulation and encoder system must determine the number of bits to be read from FIFO 110. As stated above, because convolutional coding adds an additional bit to each baud, the conventional method must calculate the value of (b1+b2xe2x88x921) and request the same number of bits from FIFO 110. According to the conventional method, b1+b2xe2x88x921 bits are received from FIFO 110 by input shift register 120 and shifted serially to the right, one bit at a time, for trellis encoding purposes. As a result, b1+b2xe2x88x921 system clock cycles are used to serially shift the necessary number of bits, i.e., one cycle per serial shift.
FIG. 1b illustrates the operation of shift register 120 according to the conventional method. Referring to FIG. 1b, assuming b1=3 and b2=6, the encoding and modulation system must first calculate the number of bits needed to be read from FIFO 110 for trellis encoding purposes. As stated above, the number of bits are calculated based on the formula b1+b2xe2x88x921=3+6xe2x88x921=8, and eight bits are read from FIFO 110 and received by input shift register 120. Assuming tone 1 consists of three bits x0, x1 and x2, and tone 2 consists of six bits y0, y1, y2, y3, y4 and y5, eight bits x0, x1, x2, y0, y1, y2, y3 and y4 are shifted serially to the right by the input shift register 120, one-by-one, for trellis encoding purposes. In other words, eight serial shifts to the right must be performed, thus, taking eight clock cycles to parse or obtain the required number of bits.
Referring back to FIG. 1a, the first three bits x0, x1 and x2 are utilized by a 16-state Wei""s convolutional encoder to generate bits v1, v0, w1 and w0 (whose derivation is beyond the scope of the present discussion). Next, trellis encoder 130 manipulates the data stream such that the four convolutionally encoded bits v1, v0, w1 and w0 are properly distributed between the two consecutive tones and concatenated with the remaining data bits for each tone to generate an output bit stream containing y0, v1 and v0 as the three bits for tone 1 and bits y4, y3, y2, y1, w1 and w0 as the six bits for tone 2. As a result, the data bits for the two tones are tied together through the 16-state Wei""s convolutional encoder. Next, the bits for tone 1 and tone 2 are shifted out by output shift register 140 for use by constellation mapper 160. Finally, the properly concatenated bits for each tone are mapped into a constellation point to complete the encoding process.
The conventional method, however, is extremely inefficient, complex and time consuming, especially when implemented in hardware. For example, the conventional method requires numerous clock cycles for calculating the required number of bits for each pair of tones. Further, the conventional method requires that bits for tone 1 and tone 2 be received and processed at the same time and that bits be shifted serially one by one, and etc. These and other shortcomings of the conventional method have formed a bottleneck in the downstream direction, i.e., in ADSL transmitters at the central sites, where the number of tones per DMT symbol or frame is very large. As stated above, the number of tones per DMT symbol in the downstream direction is 256, as opposed to 32 tones in the upstream direction, i.e., ADSL transmitters at the client side.
Accordingly, there is an intense need in the art for a new trellis encoding method and system that can eliminate the inefficiencies, complexities and other drawbacks of the conventional methods and that can remove the bottleneck in the downstream direction.
In accordance with the purpose of the present invention as broadly described herein, there is provided method and system for communications cards.
To describe various aspects of the present invention, a three-stage four-dimensional encoding system and method for DMT-based transceivers is disclosed. In the first stage, a parallel shifter shifts three bits of input data bits from a shadow register into a holding register. Next, a convolutional encoder generates encoded bits v1, v0, w1 and w0, using the three bits in the holding register. The encoded bits w1 and w0 may be registered as w1xe2x80x2 and w0xe2x80x2 for later use. In the second stage, the encoded bits v1 and v0 are provided to the inputs of the parallel shifter for parallel parsing of bits for the first tone of a pair of tones of DMT and the number of bits needed for the first tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point. In the third stage, the encoded bits w1xe2x80x2 and w0xe2x80x2 are provided to the inputs of the parallel shifter for parallel parsing of bits for the second tone of the pair of tones and the number of bits needed for the second tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point.
These and other aspects of the present invention will become apparent with further reference to the drawings and specification, which follow.